In the field of mobile communication, new communication methods are being standardized and put to practical use one after the other. When a new communication method is put to practical use, the communication method is gradually switched from the present communication method to the new communication method. Therefore, during the transitional period when switching from the present communication method to the new communication method, there are cases where a single mobile terminal supports a plurality of communication methods.
When supporting a plurality of communication methods with a single mobile terminal, an exclusive hardware component may be prepared for each communication method. However, by the method of preparing an exclusive hardware component for each communication method, the circuit scale of the mobile terminal becomes large. When the circuit scale of the mobile terminal becomes large, problems may arise, such an increase in cost and an increase in power consumption.
Furthermore, when a standardized specification is updated, the mobile terminal needs to flexibly correspond to the updated specification. By the method of preparing an exclusive hardware component for each communication method, it is not possible to quickly correspond to the updated specification.
For the above reasons, there is demand for realizing the supporting of a plurality of communication methods by a single mobile terminal, by Software Defined Radio (SDR). Software Defined Radio is for implementing the communication method by software. Specifically, a radio is constituted such that wireless processes are realized with the use of programs of a processor and a rewritable logic. By realizing the wireless processes by Software Defined Radio, it is possible to switch the communication method by changing the software, without changing the hardware.
As the method of realizing a radio by software, there is a method of using a processor and a method of using reconfigurable hardware. When realizing a radio by software, it is easy to use a processor developed by a typical method, and therefore the method of using a processor is mainstream. By using reconfigurable hardware, the configuration of the hardware is dynamically modified at the time of execution.
Meanwhile, a significantly high transmission rate has been demanded by wireless communication methods of recent years. In accordance with the increase in the transmission rate, the demanded operation processing performance of the mobile terminal is significantly increasing. Wireless communication methods of recent years include a wireless communication method of using an OFDM (Orthogonal Frequency Division Multiplex) method, which is typified by a LTE (Long Term Evolution) method. In a wireless communication method using an OFDM method, a large number of wireless resources are prepared, which are deployed in the frequency direction and the time direction, to increase the overall transmission rate.
In a process of realizing a wireless communication method such as the OFDM method, a configuration that hardly needs complex control, and that is capable of efficiently executing the repetition of a simple process, is appropriate. Here, complex control includes a branching process using operation results.
Furthermore, as a method of improving the operation performance, there is a method of combining a plurality of instructions to form one instruction of a long word, and simultaneously executing the plurality of instructions. For example, there is a technology of using VLIW (Very Long Instruction Word). VLIW is a type of an architecture of a processor, which is a method of preparing a plurality of functions, combining the instructions for operating the functions into a single instruction, and executing the single instruction of a long word.
With respect to a signal processing device, there is a device by which the circuit scale is prevented from increasing rapidly, even when the parallelism of the computing unit is increased (see, for example, Patent Document 1).    Patent Document 1: Japanese Laid-Open Patent Publication No. 2011-141791
In a method of using VLIW, there are many cases where the combined plurality of instructions do not have a direct causal relationship. In a method of using VLIW, as a result of substantially simultaneously executing a plurality of combined instructions, the execution of a certain instruction is hampered due to a stall, which is caused by another instruction that does not have a causal relationship with the certain execution. A stall means that the processing stops dues to some factor. For example, when the cycle time of the processor and the cycle time of the memory are different, the operation of the device of the faster cycle time may stop (stall). When the cycle time of the memory is slower than the cycle time of the processor, the operation of the processor stops.
Specifically, the LOAD instruction and the OPERATION instruction are substantially simultaneously executed, and when the LOAD instruction stalls, the OPERATION instruction also stalls due to the stall of the LOAD instruction.
FIG. 1 illustrates an example of a time chart of a process using VLIW (part 1). In FIG. 1, the horizontal axis indicates the time. For example, the horizontal axis indicates the “cycle”. In FIG. 1, the cycles are denoted by (1) through (10). In FIG. 1, the loaded data is used for executing an operation 1-1 (OP 1-1). That is to say, for executing the operation 1-2 (OP 1-2) and the operation 1-3 (OP 1-3), the loaded data is not directly used.
In cycle (1), a process of loading data 1 (data1) is executed (LD1).
In cycle (2), the operation 1-1 is executed, by using the data 1 loaded in cycle (1).
In cycle (3), the operation 1-2 is executed.
In cycle (4), the process of loading data 2 (data2) is executed (LD2), and the operation 1-3 is executed.
In cycle (5), the operation 1-1 is executed, by using the data 2 loaded in cycle (4).
In cycle (6), the operation 1-2 is executed.
In cycle (7), the process of loading data 3 (data3) is executed (LD3), and the operation 1-3 is executed.
In cycle (8), the operation 1-1 is executed, by using the data 3 loaded in cycle (7).
In cycle (9), the operation 1-2 is executed.
In cycle (10), the process of loading data 4 is executed (LD4), and the operation 1-3 is executed.
In the example of FIG. 1, the load process and the operation process are executed in one cycle. In the example of FIG. 1, a stall does not occur.
FIG. 2 illustrates an example of a time chart of a process using VLIW (part 2). In FIG. 2, the horizontal axis indicates the time. For example, the horizontal axis indicates the “cycle”. In FIG. 2, the cycles are denoted by (1) through (14). In FIG. 2, the loaded data is used for executing an operation 1-1 (OP 1-1). That is to say, for executing the operation 1-2 (OP 1-2) and the operation 1-3 (OP 1-3), the loaded data is not directly used.
In cycle (1) and cycle (2), the loading of the data is executed in two cycles (LD1). A stall is occurring in the first cycle among the two cycles in which the loading of the data is executed. That is to say, when reading the data from the memory, a stall of one cycle occurs.
In cycle (3), the operation 1-1 is executed, by using the data 1 (data1) read in cycle (2).
In cycle (4), the operation 1-2 is executed.
In cycle (5) and cycle (6), the loading of the data is executed in two cycles (LD2). Furthermore, in cycle (5) and cycle (6), the operation 1-3 is executed in two cycles. However, a stall is occurring in the first cycle among the two cycles in which the loading of the data is executed, and therefore a stall is occurring in the first cycle among the two cycles in which the operation 1-3 is executed. Normally, the operation instruction is executable in one cycle if the data needed for execution is provided. However, due to the impact of the stall occurring at the time of loading the data, a stall occurs in operation 1-3, and there are two cycles.
In cycle (7), the operation 1-1 is executed, by using the data 2 read in cycle (6).
In cycle (8), the operation 1-2 is executed.
In cycle (9) and cycle (10), the loading of the data is executed in two cycles (LD3). Furthermore, in cycle (9) and cycle (10), the operation 1-3 is executed in two cycles. However, a stall is occurring in the first cycle among the two cycles in which the loading of the data is executed, and therefore a stall is occurring in the first cycle among the two cycles in which the operation 1-3 is executed.
In cycle (11), the operation 1-1 is executed, by using the data 3 read in cycle (10).
In cycle (12), the operation 1-2 is executed.
In cycle (13) and cycle (14), the loading of the data is executed in two cycles (LD4). Furthermore, in cycle (13) and cycle (14), the operation 1-3 is executed in two cycles. However, a stall is occurring in the first cycle among the two cycles in which the loading of the data is executed, and therefore a stall is occurring in the first cycle among the two cycles in which the operation 1-3 is executed.
In the example of FIG. 2, the program needs to be described such that before the data, which is loaded according to a load instruction, is overwritten by a load instruction that is subsequently executed, an operation instruction using the data is executed. Specifically, before the data loaded in cycle (2) is overwritten by the data loaded in cycle (6), an operation instruction using the data loaded in cycle (2) needs to be executed. That is to say, the timings of executing the transfer instruction and the operation instruction need to be precisely defined. This is because the transfer instruction and the operation instruction affect each other. In the example of FIG. 2, a stall may frequently occur, and therefore it is difficult to describe a program such that a stall is avoided.
Furthermore, when the operation efficiency deteriorates due to a stall, a large number of hardware components are needed for realizing the same processing amount. When a large number of hardware components are used, problems arise in that the circuit scale and power consumption increase.